Novel Superconducting Qubits for Error-Corrected Processors

Summary

In this project, we develop novel superconducting qubits for error-corrected processors to enable large-scale quantum computing. Our design efforts will specifically target error-corrected architectures through a variety of paths. Possible features will include built-in parity measurements and the use of bosonic codes, such as Fock state and Cat codes, as our starting focus. Early on, we will fabricate “generation one” devices and conduct spectroscopic measurements and time-domain measurements on single qubits. Later, we will evaluate two-qubit gates and then move forward with a multi-qubit, error-corrected processor, with comprehensive error diagnostic and error suppression methods to optimize performance. The final goal is the experimental realization of a 50-qubit processor with error correction to demonstrate a practical superconducting architecture.