Cryo-CMOS to Control and Operate 2D Fault-Tolerant Qubit Network

Summary

Large-scale, fault-tolerant quantum computation requires precise and stable control of individual qubits. This project will use complementary metal-oxide-semiconductor (CMOS) technology to provide a cost-effective scalable platform for reliable and high-density control infrastructure for silicon spin qubits. We will use sub-micron CMOS technology to address device and circuit-level challenges and explore the integration of classical CMOS and quantum computing components. Since spin qubit control and measurement requires CMOS to operate at milli-Kelvin temperatures – far below the normal operating range of classical electronic devices – we will develop and calibrate compact models for MOSFETs at cryogenic temperatures, considering electrical, thermal and noise behaviors. These models will be used for cryo-CMOS design for spin qubit control operations, data readout, and communication, in a compact and scalable way at the node level. We hope to eventually implement integrated, readily scalable spin qubit control systems by bridging the classic CMOS and quantum platforms.

Figure 1. 65nm test chip for cryogenic device characterization