Summary
Leakage power in semiconductor memories, such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM), can be substantial and is one of the limits for scalability of classical electronics. This is attributed to the fact that the information stored is volatile, requiring constant refreshing, as well as reprogramming upon powering off. Spin-transfer Torque (STT) Magnetic Random Access Memory (MRAM) has the potential to meet the speed and power consumption requirements of future memory applications. Here we apply knowledge of quantum transport to improve the performance of classical devices. The goal of this project is to identify a reliable solution tolerant to fabrication variances and limited read/write margins, and to effectively integrate STT-MRAM into the broad range of Complementary Metal Oxide Semiconductor (CMOS) based technology. We aim to establish a widely accessible process to integrate MRAM cells on post-CMOS integrated circuit chips. We will do this by creating magnesium oxide based tunnel junctions with low-resistance area product and high tunnel magnetoresistance and by investigating novel STT-RAM cell design. This project marks one of the first attempts to hybridize spintronics with semiconductor devices, thereby enabling a new route towards higher-performing electronics.
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