Summary
Scaling solid-state quantum processors to a useful threshold while maintaining the requisite precision in quantum control remains a challenge. We propose a quantum metal-oxide-semiconductor (QMOS) architecture operating at cryogenic temperatures that is based on a network/node approach as a means to scalability. By working with QMOS, we benefit from the deep investments and advances that have been made in conventional CMOS device processing, and natural compatibility with CMOS integration. The architecture uses one of the most promising error correction schemes: topological stabilizer codes acting on a two-dimensional qubit arrays, also known as surface codes. The network/node approach is advantageous because it separates the surface code operation into two fundamental parts: local node operations involving a handful of qubits, which should be feasible to demonstrate in the near-term, and medium range entanglement distribution based on electron shuttling, which is challenging but can be developed in parallel. A major focus of this project is to simplify QMOS devices – reducing the number of gate electrodes per device, even down to a single electrode. The team led by Dr. Baugh with collaborators Dr. Lan Wei and Dr. Michel Pioro-Ladrière combines expertise in electrical engineering and CMOS integrated design, QMOS fabrication and physics. By testing the viability of a network/node approach, this project charts a path toward a large-scale quantum information processor in silicon.
Figure 1. (left) A false-colour scanning electron microscope image of two metal-oxide-semiconductor (MOS) quantum dots, where one is placed as the mirror image of the other. Purple represents SiO2/Si, blue represents the aluminum screening gates, and red represents the aluminum accumulation gates. In this simplified design, the tunnel coupling between the dot and the source/drain reservoirs is controlled by the physical gap between metal gates and the voltage applied to the source/drain accumulation gates. (right) Nextnano simulation of the charge density in the silicon two-dimension electron gas with top gate voltages typical of device operation. Here, the lower device is used as a charge sensor (single electron transistor) to readout the charge state of the upper dot, which can be tuned to single electron occupancy to host an electron spin qubit.
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